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12 - bit serial input multiplying cmos digital - to - analog converter DAC8043 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all rights reserved. features 12 -b it accuracy in an 8 - lead pdip and so ic package fast serial data input double data buffers low ? lsb maximum inl and 1 lsb maximum dnl max imum gain error : 2 lsb low 5 ppm/c m ax imum t empco esd r esistant low c ost available in die form app lications autocalibration s ystems process control and industrial automation programmable amplifiers and attenuators digitally controlled filters functional block dia gram 12-bit dac 12-bit dac register 12-bit shift register 12 12 DAC8043 r fb v ref ld clk sri gnd v dd i out r fb 00271-001 figure 1. general description the DAC8043 is a high accu racy 12 - bit cmos multiplying dac in a space - saving 8 - lead pdip package. featuring serial data input, double buffering, and excellent analog performance, the DAC8043 is ideal for applications where pc board space is at a premium. in addition, improved linea rity and gain error performance permit reduced parts count through the elimination of trimming components. separate input clock and load dac control lines allow full user control of data loading and analog output. the circuit consists of a 12 - bit serial - in , parallel - out shift reg ister, a 12 - bit dac register, a 12 - bit cmos dac, and control logic. serial data is clocked into the input register on the rising edge of the cl k pulse. when the new data word has been clocked in, it is loaded into the dac registe r with the ld input pin. data in the dac register is converted to an output current by the digital - to - analog converter (dac) . the fast interface timing of the DAC8043 may reduce timing design considerations while minimizing microprocessor wait states. for applications requiring an asynchronous clear function or more versatile microprocessor interface logic, refer to the ad5443 . operating from a single 5 v power supply, the DAC8043 is the ideal low power, small size, high performance solution to many application problems. it is available in a pdip package that is compatible with auto - insertion equipment. there is also a 16- lead soic pa ckag e available.
DAC8043 rev. e | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 wafe r te st l im its .......................................................................... 4 absolute maximum ratings ............................................................ 5 caution .......................................................................................... 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ..............................................7 terminology .......................................................................................9 digital section ................................................................................. 10 general circuit information ..................................................... 10 equivalent circuit analysis ...................................................... 11 dynamic performance ............................................................... 11 applications information .............................................................. 12 application ti ps ......................................................................... 12 interfacing to the mc6800 ........................................................ 14 DAC8043 interface to the 8085 ................................................ 14 DAC8043 to the 68000 interface .............................................. 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 16 revision history 1/1 1 rev. d to rev. e updated format .................................................................. universal added soic_w models .................................................... universal added table 5 .................................................................................... 6 updated outline dimensions ....................................................... 15 changes to ordering guide .......................................................... 15 3/03 data sheet c hanged from r ev . c to r ev . d. deleted 8 - lead cirdip and 16 - lead wide - body sol ...... univers al figures renumbered ................................ ........................... universal changes to absolute maximum ratings ....................................... 4 changes to ordering guide ............................................................ 4 deleted to dice characteristics ...................................................... 4 updated outline dimensions ....................................................... 11
DAC8043 rev. e | page 3 of 16 specifications electrical character istics v dd = 5 v; v ref = 10 v; i out = gnd = 0 v; t a = full temperature range specified under the absolute maximum ratings , unless otherwise noted. table 1 . parameter symbol conditions min typ max unit static accuracy resolution n 12 bits non linearity 1 inl DAC8043g ? lsb DAC8043f 1 lsb differential nonlinearity 2 dnl 1 lsb gain error 3 g fse t a = 25c 2 lsb t a = full temperature range, a ll grades 2 lsb gain tempco ( gain/?temp) 4 tc gfs 5 ppm/c power sup ply rejection ratio ( gain/v dd ) psrr v dd = 5% 0.0006 0.002 %/% output leakage current 5 i lkg t a = 25c 5 na t a = full temperature range 25 na zero scale error 6 , 7 i zse t a = 25c 0.03 lsb t a = full temperature range 0.15 lsb input resistance 8 r in 7 11 15 k ? ac performance output current settling time 4 , 9 t s t a = 25c, v ref = 0 v 0.25 1 s digital -to - analog glitch energy 4 , 10 q i out load = 100 ?, c ext = 13 pf, dac register loaded alternately with all 0s and all 1s 2 20 nvs feedthrough error (v ref to i out ) 4 , 11 ft v ref = 20 v p - p @ f = 10 khz, digital input = 0000 0000 0000 0.7 1 mv p -p t a = 25c total harmonic distortion 4 thd v ref = 6 v rms @ 1 khz, dac register loaded with all 1s C 85 db output noise voltage density 4 , 12 e n 10 hz to 100 khz between r fb and i out 17 nv/ hz digital inputs digital input high v in 2.4 v low v il 0.8 v input leakage current 13 i il v in = 0 v to +5 v 1 a input capacitance 4 , 11 c in v in = 0 v 8 pf analog outputs output capacitance 4 c out digital inputs = v ih 110 pf digital inputs = v il 80 pf timing characteristics 4 , 14 data setup time t ds t a = full temperature range 40 ns data hold time t dh t a = full temperature range 80 ns clock pulsewidth high t ch t a = full temperature range 90 ns clock pulsewidth low t cl t a = full temperatur e range 120 ns load pulsewidth t ld t a = full temperature range 120 ns lsb clock into input register to load dac register time t asb t a = full temperature range 0 ns
DAC8043 rev. e | page 4 of 16 parameter symbol conditions min typ max unit power supply supply voltage v dd 4.75 5 5.25 v supply current i dd digital inputs = v ih or v il 500 a digital inputs = 0 v or v dd 100 a 1 1/2 lsb = 0.012% of full scale. 2 all grades are monotonic to 12 bits over temperature. 3 using internal feedback resistor. 4 guaranteed by design and not tested. 5 applies to i out ; all digital inputs = 0 v. 6 v ref = 10 v; all digital inputs = 0 v. 7 calculated from worst-case r ref : i zse (in lsbs) = (r ref i lkg 4096)/v ref . 8 absolute temperature coeffi cient is less than 300 ppm/c. 9 i out load = 100 , c ext = 13 pf, digital input = 0 v to v dd or v dd to 0 v. extrapolated to ? lsb; t s = propagation delay (t pd ) + 9 where = measured time cons tant of the final rc decay. 10 v ref = 0 v, all digital inputs = 0 v to v dd or v dd to 0 v. 11 all digit inputs = 0 v. 12 calculations from en = 4 k trb where: k = boltzmann constant, j/k, r = resistance, , t = resistor temperature, k, b = bandwidth, hz. 13 digital inputs are cmos gates; i in is typically 1 na at 25c. 14 tested at v in = 0 v or v dd . wafer test limits v dd = 5 v, v ref = 10 v; i out = gnd = 0 v, t a = 25c. table 2. DAC8043gbc limit parameter 1 symbol conditions min typ max unit static accuracy resolution n 12 bits integral nonlinearity inl 1 lsb differential nonlinearity dnl 1 lsb gain error g fse using internal feedback resistor 2 lsb power supply rejection ratio psrr v dd = 5% 0.002 %/% output leakage current (i out ) i lkg digital inputs = v il 5 na reference input input resistance r in 7 15 k digital inputs digital input high v ih 2.4 v digital input low v il 0.8 v input leakage current i il v in = 0 v to v dd 1 a power supply supply current i dd digital inputs = v in or v il 500 a digital inputs = 0 v or v dd 100 a 1 electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss , yield after packaging is not guaranteed for standard product dice. consult a factory to negotiate specific ations based on dice lot qualif ications through sample lot as sembly and testing.
DAC8043 rev. e | page 5 of 16 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd ?0 .3 v to +8 v v ref to gnd 18 v v rf b to gnd 18 v digital input voltage range ? 0.3 v to v dd + 0.3 v v iout to gnd ? 0.3 v to v dd + 0.3 v operating temperature range fp version ? 40c to +85c gp version 0c to 70c junction temperature 150c storag e temperature ? 65c to +150c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. c aution 1. do not apply voltages higher than v dd or l ess than gnd potential on any terminal except v ref and r fb . 2. the digital control inputs are zener - protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. keep units in conductive foam at all times until rea dy to use. 3. use proper antistatic handling procedures. 4. ab solute maximum ratings apply to both packaged dev ices and dice . st resses above those listed under the absolute maximum ratings may cause permanent damage to the device. thermal resistance ja is speci fied for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jc unit 8- lead pdip 96 37 c/w 16- lead soic 92 27 c/w esd caution
DAC8043 rev. e | page 6 of 16 pin configuration and function descripti ons 00271-002 v ref 1 r fb 2 i out 3 gnd 4 v dd 8 clk 7 sri 6 ld 5 DAC8043 top view (not to s ca le) figure 2. 8 - lead pdip 00271-003 DAC8043 top view (not to s ca le) nc 1 nc 2 v ref 3 r fb 4 nc 16 nc 15 v dd 14 clk 13 i out 5 sri 12 gnd 6 ld 11 gnd 7 nc 10 nc 8 nc 9 nc = no connect. do not connect to this pin. figure 3 . 16 - lead wide - body so ic table 5 . pin function descriptions pin no. 8- lead pdip 16- lead soic mnemonic description 1 3 v ref dac reference voltage input pin. 2 4 r fb dac feedback resistor pin. this pin establishes voltage output for the dac by connecting to an external amplifier output. 3 5 i out dac current output. 4 6, 7 gnd ground pin. 5 11 ld load strobe, level - sensitive digital input. transfers shift - register data to dac register while active low. 6 12 sri 12- bit serial register input . d ata loads directly into the shift register msb first. extra leading bits are ignored. 7 13 clk serial clock input. positive - edge clocks data into shift register. 8 14 v dd positive power supply input. 1, 2, 8, 9, 10, 15, 16 nc do not connect to these pins.
DAC8043 rev. e | page 7 of 16 typical performance characteristics 0 ?12 ?24 ?36 ?48 ?60 ?72 ?84 ?96 ?108 ?120 1k 10k 100k 1m 10m frequency (hz) gain (db) 00271-004 v dd = 5v v ref = 100mv t a = 25c digital input = 1111 1111 1111 digital input = 0000 0000 0000 figure 4. gai n vs. frequency (output amplifier: op42) 0 ?20 ?40 ?60 ?80 ?100 ?120 10 100 1k 10k 100k frequency (hz) thd (db) 00271-005 v dd = 5v v in = 6v rms output amplifier: op42 t a = 25c figure 5. total harmonic distortion vs. frequency (multiplying mode) 1.0 0.8 0.6 0.4 0.2 0 0 1 2 3 4 v in (v) i dd (ma) 00271-006 figure 6. supply current vs. logic input voltage 0.5 0.3 0.1 ?0.1 ?0.3 ?0.4 0.4 0.2 0 ?0.2 ?0.5 0 1024 512 2048 1536 3072 2560 4095 3584 digital input code (decimal) linearity error (lsb) 00271-007 figure 7. linearity error vs. digital input code
DAC8043 rev. e | page 8 of 16 0.50 0.25 0 ?0.25 ?0.50 2 4 6 8 10 v ref (v) inl (lsb) 00271-008 figure 8. linearity error vs. reference voltage 4.0 3.0 2.0 2.4 1.0 ?0.8 1 3 5 7 9 11 13 15 v dd (v) threshold voltage (v) 00271-009 figure 9. logic threshold voltage vs. supply voltage 0.50 0.25 0 ?0.25 ?0.50 2 4 6 8 10 v ref (v) dnl (lsb) 00271-010 figure 10 . dnl error vs. reference voltage
DAC8043 rev. e | page 9 of 16 terminology integral nonlinearity (inl) this is the single most important dac specification. a nalog devices, i nc., measures inl as the maximum deviation of the analog output (from the ideal) from a straight line drawn between the end points. it is expressed as a percent of full - scale range or in terms of lsbs. refer to the analog devices glossary of ee terms for additional digital - to - analog converter definitions. interface logic information the DAC8043 has been designed for ease of operation. the timing diagram (see figure 12) illustrates the input register loading sequence. note that the most significant bit (msb) is loaded first. once the input registe r is full, the data is transferred to the dac register by taking ld momentarily low.
DAC8043 rev. e | page 10 of 16 d igital section the digital inputs of the DAC8043 ( sri, ld , and clk) are ttl compatible. the input voltage levels affect the amount of current drawn from the supply; peak supply current occurs as the digital input (v in ) passes through the transition region (see figure 6 ). maintaining the digital input voltage levels as close as pos sible to the v dd and gnd sup plies minimizes supply current consumption. the digital inputs of the DAC8043 have been designed with esd resistance incorporated through careful layout and the inclusion of input protection circuitry. figure 11 shows the input pr otection diodes and series resistor; this input structure is duplicated on each digital input. high voltage static charges applied to the inputs are shunted to the supply and ground rails through forward biased diodes. these protection diodes were designed to clamp the inputs to well below dangerous levels during static discharge conditions. g eneral c ircuit i nformation the da c8043 is a 12 - bit multiplying digital - to - analog converter (dac) with a very low temperature coefficient. it contains an r - 2r resistor ladder network, data input, control logic, and two data registers. 00271-0 11 tl/ttl/cmos inputs v dd figure 11 . digital input protection the digital circuitry forms an interface in which serial data can be loaded under microprocessor control into a 12 - bit shif t register and then transferred, in parallel, to the 12 - bit dac register. a simplified circuit of the DAC8043 is shown in figure 13, which has an inverted r - 2r ladder network consisting of silicon - chrome, highly stable (50 ppm/c) thin - film resistors, and twelve pairs of nmos current - steering switches. these switches steer binarily weighted currents into either i out or gnd; this yields a constant current in each ladder leg, regardless of digital input code. this constant current re sults in a constant input resistance at v ref equal to r. the v ref input may be driven by any reference voltage or current, ac or dc, that is within the limits stated in the absolute maximum ratings section . the twelve output curre nt - steering nmos fet switches are in series with each r - 2r resistor; they can introduce bit errors if all are of the same r on resistance value. they were designed so that the switch on resistance is binarily scaled so that the voltage drop across each switch remains constant. if, for example, switch s 1 of figure 13 w as designed with an on resistance of 10 ?, switch s 2 for 20 ? , and so on, a constant 5 mv drop would be maintained across each switch. bit 12 lsb bit 1 msb 1 bit 11 sri clk input 1 dat a loaded msb firs t. bit 2 ld t ds t dh t asb t ld t ch t cl 1 2 11 load serial data into input register load input register?s data into dac register 00271-012 figure 12 . write cycle timing diagram
DAC8043 rev. e | page 11 of 16 to further ensure accuracy across the full temperature range, permanentl y on mos s witches w ere included in series with the feedbac k resistor and the terminating resistor of the r - 2r ladder . the simplified dac circuit, figure 13 , shows the location of the series switches. these series switches are equivalently scaled to two times switch s 1 (msb) and to switch s 12 (lsb), respectively, to maintain constant relative voltage drops with varying temperature . during any testing of the resistor ladder or r feedback (such as incoming inspection), v dd must be present to turn on th ese series switches. 00271-013 20k? 20k? 20k? gnd i out r feedback s12 s3 20k? s2 20k? s1 v ref 10k? 10k? *these switches permanent ly on. 10k? 10k? bit 1 (msb) bit 2 digi tal inputs (switches shown for digi tal inputs (high)) bit 3 bit 12 (lsb) * * figure 13 . simplified dac circuit equivalent c ircuit a nalysis figure 14 shows an equivalent analog circuit for the DAC8043. the (d v ref )/r current source is code dependent and is t he current generated by the dac. the current source , i lkg , consists of surface and junction leakages and doubles approximately every 10c. c out is the output capacitance; it is the result of the n - channel mos switches and varies from 80 pf to 110 pf, depe nding on the digital input code. r o is the equivalent out - put resistance that also varies with digital input code. r is the nominal r - 2r resistor ladder resistance. 00271-014 r c out r fb i out v ref gnd i lkg d v ref r r r figure 14 . equivalent analog circuit d ynamic p erformance output impedance the output resistance of the DAC8043 , as in the case of the output capacitance, varies with the digital input code. this resistance, looking back into the i out terminal, may be between 10 k ? (the feedback resistor alone when all digital inputs are low) and 7.5 k ? (the feedback resistor in parallel with approximately 30 k ? of the r - 2r ladder network resistance when any single bit logic is high). static accuracy and dynamic performance will be affected by these variations. this variation is best illustrated by using the circuit of figure 15 and the following equation : ? ? ? ? ? ? ? ? += o fb os error r r vv 1 w here : r o is a function of the digital code and = 10 k ? for more than fo ur bits of logic 1 . = 30 k ? for any single bit of logic 1 . therefore, the offset gain varies as follows: at code 0011 1111 1111, os os 1 error v vv 2 k 10 k 10 1 = ? ? ? ? ? ? ? ? += at code 0100 0000 0000, os os 2 error v vv 3/4 k 30 k 10 1 = ? ? ? ? ? ? ? ? += the error difference is 2/3 v os . because one lsb has a weight (for v ref = 10 v) of 2.4 mv for the DAC8043, it is clearly important that v os be minimized, either by using the amplifiers nulling pins or an external nulling network or by selecting an amplifier with inherently low v os . amplifiers with suffi ciently low v os include op77 , op07 , op27 , and op42 . 00271-015 r fb v ref 2r 2r 2r etc r r r op77 v os figure 15 . simplified circuit the gain and phase stability of the output amplifier, board layout, and power supply decoupling all affect the dynamic performance. the use of a small compensation capacitor may be required when high speed operational amplifier s are used. it may be connected across the feedback resistor of the amplifier to provide the necessary phase compensation to critically damp the output. the output capacitance of the DAC8043 and the r fb resistor form a pole that must be outside the amplifi ers unity gain crossover frequency. the considerations when using high speed amplifiers are: 1. phase compensation (see figure 16 and figure 17). 2. power supply decoupling at the device socket and the use of proper grounding techniques.
DAC8043 rev. e | page 12 of 16 applications information application tips in most applications, linearity depends upon the potential of the i out and gnd p ins being equal to each other. in most applications, the dac is connected to an external op amp with its noninverting i nput tied to ground (see figure 16 and figure 17 ). the amplifier selected should have a low input bias current and low drift over temperature. the amplifiers input offset voltage should be nulled to less than 200 v (less than 10% of 1 lsb). the noninverting input of the operational amplifier should have a minimum resistance connection to ground; the usual bias current compensation resistor should not be used. this resistor can cause a variable offset voltage appea ring as a varying output error. all grounded pins should tie to a single common ground point, avoiding ground loops. the v dd power supply should have a low noise level with no transients greater than 17 v. unipolar operation (2 - quadrant) the circuit s shown in figure 16 and figure 17 may be used with an ac or dc reference voltage. the output of the circuit ranges between 0 v and approximately ?v ref (4095/4096), depending upon the digital input code. the relationship between the digital input and the analog output is shown in table 6 . the limiting parameters for the v ref range are the maximum input voltage range of the op amp or 25 v, whichever is lowest. 00271-016 op77 DAC8043 3 2 6 4 7 +15v 5v 15pf v out r fb v dd v ref i out gnd serial data input clk v ref 10v ?15v ld figure 16 . unipolar operation with high accuracy op amp (2 -quadrant) 00271-017 op42 DAC8043 2 3 6 4 7 +15v 5v 15pf v out r fb v dd v ref i out gnd serial data input clk v ref 10v r 2 50? r 1 100? ?15v ld figure 17 . unipolar operation with fast op amp and gain error trimming (2-quadrant) gain error may be trimmed by adjusting r 1 , as shown in figure 17. the dac register must first be loaded with all 1s. r 1 may then be adjusted until v out = ?v ref (4095/4096). in the case of an adjustable v ref , r 1 and r 2 may be omitted, with v ref adjusted to yield the desired full - scale output. in most applications, the DAC8043s negligible zero - scale error and very low gain error permit the elimination of th e trimming components (r 1 and the external r 2 ) without adversely affecting on circuit performance. table 6 . unipolar code table 1, 2 digital input nominal analog output msb lsb (v out as shown in figure 16 and figure 17 ) 1111 1111 1111 ? ? ? ? ? ? ? 4096 4095 ref v 1000 0000 0001 ? ? ? ? ? ? ? 4096 2049 ref v 1000 0000 0000 2 4096 2048 ref ref v v ?= ? ? ? ? ? ? ? 0111 1111 1111 ? ? ? ? ? ? ? 4096 2047 ref v 0000 0000 0001 ? ? ? ? ? ? ? 4096 1 ref v 0000 0000 0000 0 4096 0 = ? ? ? ? ? ? ? 1 nominal full scale for figure 16 and figure 17 circuits is given by ? ? ? ? ? ? ?= 4096 4095 ref v fs 2 nominal lsb magnitude for figure 16 and figure 17 circuits is given by ( ) ? ? ? ? ? ? ? = 2 or 4096 1
DAC8043 rev. e | page 13 of 16 bipolar operation (4-quadrant) figure 19 details a suggested circuit for bipolar, or offset binary, operation. table 7 shows the digital input to analog output relationship. the circuit uses offset binary coding. twos comple- ment code can be converted to offset binary by software inversion of the msb or by the addition of an external inverter to the msb input. table 7. bipolar (offset binary) code table 1, 2 digital input nominal analog output msb lsb (v out as shown in figure 19) 1111 1111 1111 ? ? ? ? ? ? ? 2048 2047 ref v 1000 0000 0001 ? ? ? ? ? ? ? 2048 1 ref v 1000 0000 0000 0 0111 1111 1111 ? ? ? ? ? ? ? 2048 1 ref v 0000 0000 0001 ? ? ? ? ? ? ? 2048 2047 ref v 0000 0000 0000 ? ? ? ? ? ? ? 2048 2048 ref v 1 nominal full scale for figure 19 circuits is given by ? ? ? ? ? ? ? 2048 2047 ref vfs 2 nominal lsb magnitude for figur e 19 circuits is given by ? ? ? ? ? ? ? 2048 1 ref vlsb resistors r 3 , r 4 , and r 5 must be selected to match within 0.01%, and they all must be of the same (preferably metal foil) type to ensure temperature coefficient matching. mismatching between r 3 and r 4 causes offset and full-scale errors, while an r 5 to r 4 and r 3 mismatch results in full-scale error. calibration is performed by loading the dac register with 1000 0000 0000 and adjusting r 1 until v out = 0 v. r 1 and r 2 may be omitted, adjusting the ratio of r 3 to r 4 to yield v out = 0 v. full scale can be adjusted by loading the dac register with 1111 1111 1111 and either adjusting the amplitude of v ref or the value of r 5 until the desired v out is achieved. analog/digital division the transfer function for the DAC8043 connected in the multiplying mode, as shown in figure 16, figure 17, and figure 19, is ? ? ? ? ? ? ????? 12 321 2 ... 222 12 321 in o aaaa vv where a x assumes a value of 1 for an on bit and 0 for an off bit. the transfer function is modified when the dac is connected in the feedback of an operational amplifier, as shown in figure 18 and becomes ? ? ? ? ? ? ? ? ? ? ? ? ??? ? ? 4 321 2 ... 222 12 321 in o aaaa v v the previous transfer function is the division of an analog voltage (v ref ) by a digital word. the amplifier goes to the rails with all bits off because division by zero is infinity. with all bits on the gain is 1 (1 lsb). the gain becomes 4096 with the lsb, bit 12, on. DAC8043 r fb v dd 5v ld sri clk v ref i out gnd digital input v in 00271-019 op42 2 3 6 v out figure 18. analog/digital divider 00271-018 v out control inputs serial data input analog common v in r 2 50? r 3 10k ? 5v r 4 20k ? r 5 20k ? r 1 100 ? c 1 10.33pf 1/2 op200 a 2 DAC8043 r fb v dd v ref i out gnd control bits sri 1/2 op200 a 1 figure 19. bipolar operation (4-quadrant, offset binary)
DAC8043 rev. e | page 14 of 16 interfacing to the m c6800 as shown in figure 20 , the DAC8043 may be interfaced to the mc 6800 by successively executing memory write instructions while manipulating the data between w rites , so that each write presents the next bit. in this example , the most significant bits are found in the 0000 and 0 001 memory locations . the four msbs are found in the lower half of 0000 and the eight lsbs in 0001. the data is taken from the db 7 line. the serial data loading is t riggered by the clk pulse, which is asserted by a decoded memory write to the 2000 memory location , r/ w , and 2. a write to a ddress location 4000 transfers data from the input register to the dac register. 00271-020 74ls138 address decoder a 0 a 0 a 15 db 0 db 7 e 1 e 3 e 2 a 2 sri clk ld DAC8043* 16-bit d at a bus r/w 2 8-bit d at a bus mc6800 *analog circuitry omitted for simplicity. figure 20 . DAC8043 to mc6800 interface DAC8043 interface to the 8085 the interface of the dac80 43 to the 8085 microprocessor is shown in figure 21 . note that the sod line of the micro - processor is used to present data serially to the dac. data is clocked into the DAC8043 by executing memory write instructions. the clock in put is generated by decoding address 8000 and wr . data is loaded into the dac register with a memory write instruction to address a000. serial data supplied to the DAC8043 must be present in the rig ht - justified format in register h and r egister l of the microprocessor . 00271-021 a 0 a 15 ad 0 ad 7 (8) (8) ale sod sri *analog circuitry omitted for simplicity. clk ld DAC8043* address bus (16) dat a 8085 8212 wr 74ls138 address decoder a 0 e 1 e 3 5v e 2 a 2 figure 21 . DAC8043 to 8085 interface DAC8043 to the 68000 interface the interface of the DAC8043 to the 68000 microprocessor is shown in figure 22 . s erial data to the dac is taken from one of the microprocessors data bus lines. 00271-022 a 1 a 23 as vma vpa uds db 0 db 15 sri clk ld DAC8043* address bus dat a bus 1/4 74hc125 68000 micro- processor *analog circuitry omitted for simplicity. address decode cs + figure 22 . DAC8043 to 68000 microprocessor interface
DAC8043 rev. e | page 15 of 16 outline dimensions compliant t o jedec s t andards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equi v alents for reference on ly and are not appropri a te for use in design. corner leads m ay be configured as whole or half leads. 070606- a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) sea ting plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0. 1 15 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7. 1 1) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0. 1 15 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 23 . 8- lead plastic dual in - line package [pdip] narrow body (n- 8) dimensions shown in inches and (millimeters) controlling dimensions a re in millimeters; inch dimensions (in parent heses) are rounded-off millimeter equivalents for r eference only and are not appropriate for use in d esign. c ompliant to jedec standards ms-013-aa 10 .50 ( 0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 24 . 16 - lead standard small outline package [soic_w] wide body (rw - 16) dimensions shown in millimeters and (inches)
DAC8043 rev. e | page 16 of 16 ordering guide model 1 , 2 relative accuracy temperature r ange package description package option DAC8043fp 1 lsb ? 40c to +85c 8- lead pdip n-8 DAC8043fpz 1 lsb ? 40c to +85c 8- lead pdip n-8 DAC8043fsz 1 lsb ? 40c to +85c 16- lead soic_w rw -16 DAC8043gp ? lsb 0c to 70c 8- lead pdip n-8 DAC8043gpz ? lsb 0c to 70c 8- lead pdip n-8 1 z = rohs compliant part. 2 all commercial and industrial temperature range parts are available with burn - in. ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00271 -0- 1/11(e)

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